UVMarvel: an Automated LLM-aided UVM Machine for Subsystem-level RTL Verification
Junhao Ye, Dingrong Pan, Hanyuan Liu, Yuchen Hu, Jie Zhou + 5 more
TLDR
UVMarvel automates UVM testbench creation for subsystem-level RTL verification using LLMs, significantly boosting efficiency and coverage.
Key contributions
- Automates UVM testbench construction for subsystem-level RTL using LLMs.
- Introduces an Intermediate Representation (IR) and Bus Protocol Library for accurate testbench generation.
- Employs a Signal Tracker and Verilog Patching Library for LLM-based stimuli refinement.
- Achieves 95.65% average code coverage and reduces verification time from days to 4.5 hours.
Why it matters
IC verification is a major bottleneck in chip development, consuming significant effort. UVMarvel addresses this by automating complex UVM testbench creation, drastically cutting down manual effort and time. This innovation promises to accelerate chip design cycles and improve verification quality.
Original Abstract
Verification presents a major bottleneck in Integrated Circuit (IC) development, consuming nearly 70% of total effort. While the Universal Verification Methodology (UVM) improves reuse through structured verification environments, constructing subsystem-level UVM testbenches and generating high-quality stimuli still require extensive manual coding, repeated EDA tool runs, and deep protocol and micro-architectural expertise. We present UVMarvel, an automated verification framework that leverages Large Language Models (LLMs) to build UVM testbenches for subsystem-level RTL.UVMarvel introduces an Intermediate Representation (IR) and a Bus Protocol Library to translate heterogeneous specifications into protocol-correct subsystem-level UVM testbenches, and employs a Signal Tracker and a Verilog Patching Library to guide LLM-based stimuli refinement. UVMarvel is the first framework capable of automatically constructing subsystem-level UVM testbenches across mainstream bus protocols, and it achieves an average code coverage of 95.65%, while reducing verification time from several human working days to a 4.5-hour automated execution.
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