Pulse Shaping to Mitigate the Impact of Device Imperfections in Field-Free Switching Using Combined Spin-Orbit and Spin-Transfer Torques
Kuldeep Ray, Jérémie Vigier, Sylvain Martin, Chloé Bouard, Nicolas Lefoulon + 2 more
TLDR
This paper shows that STT pulse shaping can reduce write errors and improve robustness in SOT-MRAM, mitigating device imperfections in field-free switching.
Key contributions
- Investigated write error rates in SOT+STT field-free switching for top-pinned SOT-MRAM.
- Identified STT-induced backhopping and switching asymmetry in experimental devices.
- Developed a macrospin model revealing a new loss-of-determinism regime.
- Experimentally showed STT pulse shaping reduces write errors and improves robustness.
Why it matters
Field-free SOT-MRAM is crucial for industrial adoption, but combined SOT+STT switching faces reliability issues like backhopping and asymmetry. This work identifies these challenges and proposes STT pulse shaping as an effective mitigation strategy. This significantly improves switching robustness, advancing SOT-MRAM's practical deployment.
Original Abstract
Combining spin-orbit (SOT) and spin-transfer torques (STT) provides a practical approach for field-free switching in spin-orbit torque magnetic random-access memory (SOT-MRAM), a prerequisite for industrial deployment, but can compromise reliability through phenomena such as backhopping, especially in top-pinned stacks commonly used for SOT-MRAM. We investigate the write error rate (WER) of combined SOT + STT switching in top-pinned devices that are not optimized for STT switching. Experiments reveal clear indications of STT-induced backhopping and a pronounced field-free SOT switching asymmetry between AP-to-P and P-to-AP transitions. Our macrospin model, using two coupled Landau Lifshitz Gilbert equations for the free and the reference layers, qualitatively reproduces this asymmetry and reveals an intermediate loss-of-determinism regime in addition to the well-known backhopping region. Based on these simulations, we propose mitigation strategies and experimentally demonstrate that STT pulse shaping reduces WER and improves switching robustness in the presence of device imperfections.
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