ArXiv TLDR

Focus Session: Hardware and Software Techniques for Accelerating Multimodal Foundation Models

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2604.21952

Muhammad Shafique, Abdul Basit, Muhammad Abdullah Hanif, Alberto Marchisio, Rachmad Vidya Wicaksana Putra + 1 more

cs.LGcs.AIcs.ARcs.NEcs.RO

TLDR

This paper presents a multi-layered hardware/software co-design methodology to efficiently accelerate multimodal foundation models, reducing computational and memory needs.

Key contributions

  • Multi-layered hardware/software co-design for transformer blocks, reducing computation and memory.
  • MFM compression via hierarchy-aware mixed-precision quantization and structural pruning.
  • Optimizes operations using speculative decoding, model cascading, and co-optimization of parameters.
  • Dataflow optimization for hardware and specialized accelerators for transformer workloads.

Why it matters

Multimodal Foundation Models are computationally intensive. This methodology provides a comprehensive approach to accelerate MFMs through hardware/software co-design and various optimizations, making them more efficient. This enables broader deployment and new applications, demonstrated in medical AI and code generation.

Original Abstract

This work presents a multi-layered methodology for efficiently accelerating multimodal foundation models (MFMs). It combines hardware and software co-design of transformer blocks with an optimization pipeline that reduces computational and memory requirements. During model development, it employs performance enhancements through fine-tuning for domain-specific adaptation. Our methodology further incorporates hardware and software techniques for optimizing MFMs. Specifically, it employs MFM compression using hierarchy-aware mixed-precision quantization and structural pruning for transformer blocks and MLP channels. It also optimizes operations through speculative decoding, model cascading that routes queries through a small-to-large cascade and uses lightweight self-tests to determine when to escalate to larger models, as well as co-optimization of sequence length, visual resolution & stride, and graph-level operator fusion. To efficiently execute the model, the processing dataflow is optimized based on the underlying hardware architecture together with memory-efficient attention to meet on-chip bandwidth and latency budgets. To support this, a specialized hardware accelerator for the transformer workloads is employed, which can be developed through expert design or an LLM-aided design approach. We demonstrate the effectiveness of the proposed methodology on medical-MFMs and on code generation tasks, and conclude with extensions toward energy-efficient spiking-MFMs.

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